The present invention relates generally to integrated circuits, and, more particularly, to a voltage regulation system for an integrated circuit.
Many integrated circuits (ICs) today including system-on-chips (SoCs) integrate various digital and analog components on a single chip. Such ICs also include different power domains including high and low power domains. The high power domain includes components that operate when the IC is in a HIGH power mode and are powered down when the IC is in a LOW power mode. The low power domain includes components that operate when the IC is in the HIGH and LOW power modes. ICs with multiple power domains require multiple power supplies that are served by voltage regulators. The voltage regulators provide different voltages to the components in the high and low power domains based on the IC mode of operation.
FIG. 1 is a schematic block diagram of a conventional integrated circuit (IC) 100 that is operable in both HIGH and LOW power modes and includes a low voltage regulator 102 (hereinafter “LV regulator”), a high voltage regulator 104 (hereinafter “HV regulator”), a low power low voltage regulator 106 (hereinafter “LP_LV regulator”), a low power domain 108, a high power domain 110, and a switch 112. The LV and HV regulators 102 and 104 are connected to an external power supply (not shown). The switch 112 is connected between the LV regulator 102 and the low power domain 108. The LV regulator 102 provides a first regulated voltage VLV to both the low and high power domains 108 and 110 when the IC 100 is in the HIGH power mode and is switched off when the IC 100 is in the LOW power mode. The HV regulator 104 generates a second regulated voltage VHV when the IC 100 is in either of the HIGH or LOW power modes. The LP_LV regulator 106 receives the second regulated voltage VHV and provides a third regulated voltage VLP—LV to the low power domain 108 when the IC 100 is in the LOW power mode. The LP_LV regulator 106 is an internal low power regulator implemented using a p-type, metal-oxide semiconductor (PMOS) transistor 114 having its source and body terminals connected together. An intrinsic diode 116 is formed between the drain and source or body terminals of the PMOS transistor 114. In order to avoid undesirable circuit behavior, the intrinsic diode 116 is usually kept reverse biased (e.g., VLP—LV<VHV).
The low power domain 108 functions in both the HIGH and LOW power modes, while the high power domain 110 functions in the HIGH power mode and is powered down in the LOW power mode. The switch 112 is closed when the IC 100 is in the HIGH power mode, which allows the LV regulator 102 to provide the first regulated voltage VLV to the low power domain 108.
In both the HIGH and LOW power modes, the first regulated voltage VLV is lower than the second regulated voltage VHV. Therefore, the intrinsic diode 116 is reverse biased because its body terminal is at a higher potential than its drain terminal. However, conditions such as power-on-reset (POR), sudden failure, and accidental resets may cause the IC 100 to reset, causing the IC 100 to power-on and transition to the HIGH power mode (referred to as power-up). During power-up, the output voltage of the LV regulator 102 may reach a steady-state voltage level before the output voltage of the HV regulator 104. Therefore, the output voltage of the LV regulator 102 may be higher than the output voltage of the HV regulator 104 for a transient period. Since the switch 112 is closed during power-up, the intrinsic diode 116 in the LP_LV regulator 106 is forward biased, causing a short-circuit path between the LV and HV regulators 102 and 104, by way of the switch 112 and the LP_LV regulator 106. When such a condition occurs, a high supply current is drawn from the LV regulator 102, which can damage some internal components of the IC 100.
One technique to overcome the aforementioned problem is to employ a specific power sequence. Power sequencing controls the order in which the LV and HV regulators 102 and 104 are powered up or down. However, power sequencing is not always desirable because it requires complex applications to prevent the aforementioned problem. Another known technique entails applying a high voltage to a well region of the PMOS transistor 114, which renders the intrinsic diode 116 non-conductive and thus prevents the short-circuit path. However, applying this high voltage increases power consumption of the IC 100.
Therefore, it would be advantageous to have a voltage regulating system in an integrated circuit that avoids damaging internal components of the integrated circuit caused by the aforementioned problem.